(a) Field of the Invention
The present invention concerns an insulated-gate type transistor, and a semiconductor integrated circuit structure using such transistor, and more particularly it pertains to an insulated-gate type transistor, such as insulated-gate type static induction transistor, having substantially reduced series resistance and gate capacitance and being easy to manufacture and exhibiting a non-saturating current versus voltage characteristic, and also pertains to a semiconductor integrated circuit structure using such transistors.
(b) Description of the Prior Art
A static induction transistor (hereinafter to be referred to briefly as SIT) whose drain current continues to increase with an increase in its drain voltage has been proposed by Jun-ichi NISHIZAWA in U.S. patent application Ser. No. 817,052 and by Jun-ichi NISHIZAWA et al in U.S. patent application Ser. No. 576,541.
An SIT has been found to be superior in each of its various properties including high power and large current capacity, high breakdown voltage, low distortion, low noise, low power dissipation, and high-speed operation. This SIT is ia transistor which is abundant in excellent properties including its thermal characteristic, when compared with known bipolar transistors and known field effect transistors. The superiority of SIT when employed either as a discrete element or as an element for use in integrated circuit has been proved already, and thus new fields of its application are being developed in various technological fields. Since the input impedance of the SIT is high, it can be directly coupled to a preceding stage of circuitry without any amplifying stage. Furthermore, since the SIT requires only a little driving power, it contributes to enhancing packing density. Moreover, because the SIT exhibits a non-saturating type current versus voltage characteristic, and because the it has a large transconductance, a large fan-out can be obtained. Thus, the SIT is extremely suitable for use in integrated circuit.
Basic structures of insulated-gate (IG) SIT (MOS-SIT and MIS-SIT) which operate either in the so-called enhancement mode (E-mode) or the so-called depletion mode (D-mode) have been elucidiated already by J. NISHIZAWA et al in, for example, U.S. patent application Ser. No. 867,298, and by J. NISHIZAWA in Japanese Patent Application Laying-open No. 53-99778 entitled "MOS, MIS Static Induction Transistor", and by J. NISHIZAWA in U.S. Pat. No. 4,334,235, and also by J. NISHIZAWA in Japanese Patent Application Laying open No. 53-113483 entitled "MOS, MIS Static Induction Transistor".
An insulated-gate type SIT (hereinafter to be referred to as IG-SIT) having a reduced gate capacitance and a large transconductance has been proposed by J. NISHIZAWA et al also in their U.S. patent application Ser. No. 867,298. An example of its structure in case of an n-channel IG-SIT is shown in the attached FIG. 1. In this Figure, n.sup.+ type regions 1 and 3 represent a source region and a drain region. A p.sup.- type region, 2 represents a channel-forming region part of which will be used as a channel. Numeral 4 represents a gate electrode, 5 a p type substrate, 5' a p type region protruding from the substrate 5 and touching the source region 1, and 6 an insulating layer made with, for example, SiO.sub.2, Al.sub.2 O.sub.3, Si.sub.3 N.sub.4 or AlN, or their mixture, or their composite insulating layer. Also, numerals 1' and 3' represent a source electrode and a drain electrode.
In case a typical drain voltage applied is assumed to be V.sub.D, the impurity concentration of the p.sup.- type region 2 is selected to be a value in the vicinity of 2.epsilon.(V.sub.D +V.sub.bi)el.sup.2, or a value slightly higher than that, wherein .epsilon. represents the dielectric constant of the p.sup.- type region 2, e represents the magnitude of electronic charge, l represents the source-to-drain distance, and V.sub.bi represents the built-in potential at the n.sup.+ p.sup.- junction between the channel region 2 and the drain region 3. The channel width in the vicinity of the source region is narrowed by bulging upwardly the p type region 5' to ensure that the current flowing from the source region into the drain region can be effectively controlled by the gate electrode 4.
The structure shown in FIG. 1 is such that the p type protruding portion 5' requires to be formed either by epitaxial growth of a p.sup.- type region on top of a selectively etched p type substrate 5 and 5', or by carrying out selective diffusion of an n type impurity into the p type substrate to locally convert this p type region into a p.sup.- type region 2 and to leave the rest of the p type region 5 and 5' as it was, or by forming a p type embedded-type protrusion 5' by ion-implantation into a preliminarily epitaxially grown p.sup.- type region 2 located on the p type substrate 5, etc. Thus, the manufacturing process of this structure requires inconvenient additional steps, and accordingly the cost of manufacture becomes all the more expensive.